LPUART3=0, LPUART4=0, QSPI=0, DAC0=0, EMVSIM1=0, LPUART2=0, LPUART0=0, TPM2=0, FLEXIO=0, LTC=0, EMVSIM0=0, TPM1=0, LPUART1=0
System Clock Gating Control Register 2
| LPUART0 | LPUART0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| LPUART1 | LPUART1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| LPUART2 | LPUART2 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| LPUART3 | LPUART3 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| TPM1 | TPM1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| TPM2 | TPM2 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| DAC0 | DAC0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| LTC | LTC Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| EMVSIM0 | EMVSIM0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| EMVSIM1 | EMVSIM1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| LPUART4 | LPUART4 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| QSPI | QSPI Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| FLEXIO | FlexIO Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |